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general description the MAX6892/max6893/max6894 pin-selectable, mul- tivoltage supply sequencers/supervisors monitor sever- al voltage-detector inputs and one watchdog input, asserting the respective voltage detector or watchdog output when the inputs drop below the configured volt- age thresholds or the watchdog timer expires. the MAX6892 features eight voltage detector inputs and 10 outputs. the max6893 features six voltage-detector inputs and eight outputs, while the max6894 features four voltage detector inputs and six outputs. a reset output ensures all monitored inputs are above the set thresholds. the voltage detector outputs are configured as open drain. manual reset and margin disable inputs offer additional flexibility. the thresholds of the MAX6892/max6893/max6894 are selected through five logic inputs (th0?h4). the logic on these five inputs selects the supply voltage tolerance (5% or 10%) and one of 32 factory-set thresholds settings. watchdog and reset timeout periods can use factory default settings or are independently adjustable by con- necting external capacitors. when any of the monitored voltages falls below its threshold, the respective output asserts and remains asserted for 6.25ms (typ) after the monitored voltage exceeds the threshold. the outputs can be connected to the shutdown or enable inputs of dc-dc regulators to provide turn-on power sequencing to ensure proper system initialization. the MAX6892 is available in a 5mm x 5mm x 0.8mm, 32-pin, thin qfn package, while the max6893/ max6894 are available in a 5mm x 5mm x 0.8mm, 28- pin, thin qfn package. the MAX6892/max6893/ max6894 are specified to operate over the extended temperature range (-40? to +85?) applications telecommunication/central office systems networking systems servers/workstations base stations storage equipment multimicroprocessor/voltage systems features ? pin-selectable or user-adjustable voltage detector thresholds ? dedicated reset and wdo outputs ? capacitor-adjustable reset and watchdog timeout periods ? factory-default reset and watchdog timeout periods ? up to eight independent, open-drain power-good outputs ? enable margining disable and manual reset controls ? -40? to +85? operating temperature range ? small 5mm x 5mm thin qfn package ? few external components ? ?% threshold accuracy MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors ________________________________________________________________ maxim integrated products 1 part temp range pin- package pkg code MAX6892 etj -40? to +85? 32 thin qfn t3255-4 max6893 eti -40? to +85? 28 thin qfn t2855-8 max6894 eti -40? to +85? 28 thin qfn t2855-8 ordering information 19-3596; rev 0; 2/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical operating circuit appears at end of data sheet. pin configurations 32 31 30 29 28 27 26 910111 2131415 18 19 20 21 22 23 24 7 6 5 4 3 2 1 MAX6892 thin qfn top view pg3 pg2 pg4 gnd pg5 pg6 pg7 8 *exposed paddle *exposed pad internally connected to gnd. pg8 pg1 wdi in1 in2 in3 in4 in5 25 in6 in7 in8 dbp v cc enable srt swt 17 th4 th2 th1 16 th3 th0 mr margin wdo reset pin configurations continued at end of data sheet.
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in1 = v in6 ? in8 = gnd, v in2 ? in5 = 2.7v to 5.5v, wdi = enable = gnd, th0?h4 = margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1 and 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) pg_, reset , wdo .................................................-0.3v to +14v in1?n8, th0?h4, enable , wdi, mr , margin , srt, swt, v cc .....................................................-0.3v to +6v dbp ..........................................................................-0.3v to +3v input/output current (all pins)..........................................?0ma continuous power dissipation (t a = +70?) 28-pin thin qfn (derate 21.3mw/? above +70?).............................................................1702mw 32-pin thin qfn (derate 21.3mw/? above +70?)............................................................1702mw maximum junction temperature .....................................+150? operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating voltage range (note 3) voltage on either one of in2?n5 or v cc that guarantees the part is fully operational 2.7 5.5 v undervoltage lockout v uvlo for 1v < (v in2 v in5 or v cc ) < v uvlo , pg_ are pulled down to gnd with a 10? current 2.5 v digital bypass voltage v dbp no load 2.48 2.55 2.67 v supply current i cc v in2 = 5.5v, v in1 , v in3 v in8 = gnd, no load 0.9 1.1 ma t a = +25? to +85? -1 +1 threshold accuracy (table 2) v th in1?n8, in_ falling t a = -40? to +85? -2 +2 % v th threshold hysteresis v th-hys 0.3 % v th threshold tempco ? v th /? 10 ppm/? in1, in6?n8 input leakage current i in in2?n5 set as adjustable thresholds -50 +50 na in2?n5 input impedance r in2?n5 for in_ voltages < the highest in_ supply or < v cc and thresholds are not set as adjustable 290 400 555 k ? power-up delay t d-po v cc v uvlo 3ms in_ to pg_ delay t d-r in_ falling/rising, 100mv overdrive 25 ? pg_ timeout period t pg 5.625 6.25 6.875 ms reset default timeout period t rp v srt = v cc 180 200 220 ms reset adjustable timeout period t rp-adj c srt = 47nf 135 207 280 ms srt adjustable timeout current i srt v srt = gnd 180 230 280 na
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in1 = v in6 ? in8 = gnd, v in2 ? in5 = 2.7v to 5.5v, wdi = enable = gnd, th0?h4 = margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1 and 2) parameter symbol conditions min typ max units srt default timeout threshold v srt-def v srt v srt-def , selects reset default timeout 1.1 1.25 1.5 v srt adjustable timeout threshold v srt-adj (note 4) 0.95 1.0 1.05 v srt adjustable timeout discharge threshold v srt-dis (note 5) 100 mv srt adjustable timeout output low discharge current i srt-dis v srt = 0.3v 0.7 ma pg_, reset , wdo output low v ol i sink = 4ma, output asserted 0.4 v pg_, reset , wdo output initial pulldown current i uv v cc < v uvlo , v pg _ , reset , wdo = 0.8v 10 40 ? pg_, reset , wdo output open- drain leakage current i lkg output high impedance -1 +1 ? v il 0.6 mr , margin , enable , th0?h4, wdi input voltage v ih 1.4 v mr input pulse width t mr 1s mr glitch rejection 100 ns mr to reset delay t d- mr 2s mr to dbp pullup current i mr v mr = 1.4v 5 10 15 a margin to dbp pullup current i margin v margin = 1.4v 5 10 15 a enable to pg_ delay t d-enpg 200 ns enable pulldown current v enable = 0.6v 5 10 15 a
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in1 = v in6 ? in8 = gnd, v in2 ? in5 = 2.7v to 5.5v, wdi = enable = gnd, th0?h4 = margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1 and 2) parameter symbol conditions min typ max units th0?h4 input current -1 +1 ? wdi pulldown current i wdi v wdi = 0.6v 5 10 15 a wdi input pulse width 50 ns initial mode 92.16 102.4 112.64 watchdog default timeout period t wd v swt = v cc normal mode 1.44 1.6 1.76 s initial mode 53.7 82.5 111.9 watchdog adjustable timeout period t wd-adj c swt = 0.33? normal mode 0.93 1.43 1.94 s swt adjustable timeout current i swt v swt = gnd 180 230 280 na swt default timeout threshold v swt-def v swt v swt-def , selects watchdog default timeout period 1.1 1.25 1.5 v swt adjustable timeout threshold v swt-adj (note 4) 0.95 1.0 1.05 v swt adjustable timeout discharge threshold v swt-dis (note 5) 100 mv swt adjustable timeout output low discharge current i swt-dis v swt = 0.3v 0.7 ma note 1: 100% production tested at t a = +25? and t a = +85?. specifications at t a = -40? are guaranteed by design. note 2: device may be supplied from any one of in2?n5, or v cc . note 3: the internal supply voltage, measured at v cc , equals the maximum of in2?n5. note 4: external capacitor is charged by i s_t when v s_t-dis < v s_t < v s_t-adj . note 5: external capacitor is discharged by i s_t-dis down to v s_t-dis after v s_t reaches v s_t-adj .
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 5 t ypical operating characteristics (v in1 = v in6 ? in8 = gnd, v in2 ? in5 = 2.7v to 5.5v, wdi = gnd, th0?h4 = margin = mr = dbp. typical values are at t a = +25?.) supply current vs. supply voltage (in2?n5) MAX6892 toc01 supply voltage (v) supply current (ma) 5.0 4.5 4.0 3.5 3.0 0.6 0.7 0.8 0.9 1.0 1.1 0.5 2.5 5.5 t a = +85 c t a = -40 c t a = +25 c 5.0 4.5 4.0 3.5 3.0 2.5 5.5 supply current vs. supply voltage (v cc ) MAX6892 toc02 supply voltage (v) supply current (ma) 0.6 0.7 0.8 0.9 1.0 1.1 0.5 t a = +85 c t a = -40 c t a = +25 c normalized pg_ timeout period vs. temperature MAX6892 toc03 temperature ( c) normalized pg_ timeout period 60 35 10 -15 0.8 0.9 1.0 1.1 1.2 1.3 0.7 -40 85 in_to pg_ propagation delay ( s) 12 14 16 18 20 22 24 26 28 30 10 in_to pg_ propagation delay vs. temperature MAX6892 toc04 temperature ( c) 60 35 10 -15 -40 85 100mv overdrive normalized reset timeout period 0.985 0.990 0.995 1.000 1.010 1.005 1.015 1.020 0.980 normalized default reset timeout period vs. temperature MAX6892 toc05 temperature ( c) 60 35 10 -15 -40 85 t rp = 200ms v srt = v cc 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 0.90 normalized reset timeout period normalized adjustable reset timeout period vs. temperature MAX6892 toc06 temperature ( c) 60 35 10 -15 -40 85 t rp = 200ms c srt = 47nf normalized watchdog timeout period 0.97 0.98 0.99 1.00 1.02 1.01 1.03 1.04 0.96 normalized default watchdog timeout period vs. temperature MAX6892 toc07 temperature ( c) 60 35 10 -15 -40 85 t rp = 1.6s v swt = v cc normalized watchdog timeout period 0.85 0.90 0.95 1.00 1.10 1.05 1.15 1.20 0.80 normalized adjustable watchdog timeout period vs. temperature MAX6892 toc08 temperature ( c) 60 35 10 -15 -40 85 t rp = 1.6s c swt = 0.33 f 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 0.995 normalized in_ threshold normalized in_ threshold vs. temperature MAX6892 toc09 temperature ( c) 60 35 10 -15 -40 85
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 6 _______________________________________________________________________________________ 100 10 1 1000 maximum in_ transient vs. in_ threshold overdrive MAX6892 toc10 in_ threshold overdrive (mv) maximum transient duration ( s) 25 50 75 100 125 150 175 200 0 pg_ assertion occurs output voltage low vs. sink current MAX6892 toc11 i sink (ma) v ol (mv) 13 14 12 10 11 3456789 12 50 100 150 200 250 300 350 400 450 500 0 015 mr to reset propagation delay (ns) 1.85 1.90 1.95 2.00 2.10 2.05 2.15 2.20 1.80 mr to reset propagation delay vs. temperature MAX6892 toc12 temperature ( c) 60 35 10 -15 -40 85 reset timeout period vs. c srt MAX6892 toc13 c srt (nf) timeout period (ms) 100 10 1 1 10 100 1000 10,000 0.1 0.1 1000 watchdog timeout period vs. c swt MAX6892 toc14 c swt (nf) timeout period (ms) 100 10 1 1 10 100 1000 10,000 0.1 0.1 1000 t ypical operating characteristics (continued) (v in1 = v in6 ? in8 = gnd, v in2 ? in5 = 2.7v to 5.5v, wdi = gnd, th0?h4 = margin = mr = dbp. typical values are at t a = +25?.)
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 7 pin MAX6892 max6893 max6894 name function 11 1 pg2 open-drain, power-good output 2. pg2 asserts low when the voltage input at in2 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg2 deasserts with a factory preset timeout period of 6.25ms. 22 2 pg3 open-drain, power-good output 3. pg3 asserts low when the voltage input at in3 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg3 deasserts with a factory preset timeout period of 6.25ms. 33 3 pg4 open-drain, power-good output 4. pg4 asserts low when the voltage input at in4 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg4 deasserts with a factory preset timeout period of 6.25ms. 44 4 gnd ground 55 pg5 open-drain, power-good output 5. pg5 asserts low when the voltage input at in5 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg5 deasserts with a factory preset timeout period of 6.25ms. 66 pg6 open-drain, power-good output 6. pg6 asserts low when the voltage input at in6 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg6 deasserts with a factory preset timeout period of 6.25ms. 7 pg7 open-drain, power-good output 7. pg7 asserts low when the voltage input at in7 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg7 deasserts with a factory preset timeout period of 6.25ms. 8 pg8 open-drain, power-good output 8. pg8 asserts low when the voltage input at in8 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg8 deasserts with a factory preset timeout period of 6.25ms. 97 7 reset open-drain, active-low reset output stage. reset asserts low when any monitored input (in_) is below the selected threshold or manual reset ( mr ) is pulled low. reset remains low for the reset timeout period after all reset- causing conditions are cleared, and then deasserts. 10 8 8 wdo open-drain, active-low watchdog output stage. if wdi remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and the wdo output asserts low. the internal watchdog timer clears whenever reset is asserted or wdi sees a rising or falling edge. connect wdo to mr to automatically assert the reset output after each watchdog timeout fault. 11 9 9 margin margin input. margin holds pg_, reset , and wdo in their existing states when driven low. leave margin unconnected or connect to dbp if unused. margin overrides mr if both assert at the same time. margin is internally pulled up to dbp through a 10? current source. 12 10 10 mr active-low manual reset input. pull mr low to assert reset . reset remains asserted for its preset/adjustable reset timeout period when mr is driven/pulled high. mr is internally pulled up to dbp through a 10? current source. 13 11 11 th0 threshold selection input 0. logic input to select desired thresholds. connect th0 to gnd or dbp. see table 2 for available thresholds. input has no internal pullup or pulldown. pin description
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 8 _______________________________________________________________________________________ pin description (continued) pin MAX6892 max6893 max6894 name function 14 12 12 th1 threshold selection input 1. logic input to select desired thresholds. connect th1 to gnd or dbp. see table 2 for available thresholds. input has no internal pullup or pulldown. 15 13 13 th2 threshold selection input 2. logic input to select desired thresholds. connect th2 to gnd or dbp. see table 2 for available thresholds. input has no internal pullup or pulldown. 16 14 14 th3 threshold selection input 3. logic input to select desired thresholds. connect th3 to gnd or dbp. see table 2 for available thresholds. input has no internal pullup or pulldown. 17 15 15 th4 threshold selection input 4. logic input to select desired thresholds. connect th4 to gnd or dbp. see table 2 for available thresholds. input has no internal pullup or pulldown. 18 16 16 swt watchdog timeout adjust input. connect swt to v cc to select the default watchdog timeout period. connect an external capacitor between swt and gnd to adjust the watchdog timeout period. the adjustable timeout period is calculated by t wp = 4.348e6 x c swt (t wp in seconds and c swt in farads). disable the watchdog timer by connecting swt to gnd. 19 17 17 srt reset timeout adjust input. connect srt to v cc to select the default reset timeout period. connect an external capacitor between srt and gnd to adjust the reset timeout period. the adjustable timeout period is calculated by t rp = 4.348e6 x c swt (t rp in seconds and c srt in farads). 20 18 18 enable active-low, pg_ enable input. pull enable high to force all pg_ outputs low. pg_ outputs remain asserted for their timeout period when enable is driven/pulled low. enable is internally pulled down to gnd through a 10? current sink. 21 19 19 v cc internal supply voltage. bypass v cc to gnd with a 1? capacitor as close to the device as possible. v cc supplies power to the internal circuitry. v cc is internally powered from the highest of the monitored in2?n5 voltages. do not use v cc to supply power to external circuitry. to externally supply v cc, see the powering the MAX6892/max6893/max6894 section ) . 22 20 20 dbp digital bypass voltage. dbp supplies power to the output stages. bypass dbp to gnd with a 1? capacitor as close to the device as possible. do not use dbp to supply power to external circuitry. 23 in8 input voltage 8. select undervoltage threshold using th0?h4. see table 2. for improved noise immunity, bypass in8 to gnd with a 0.1? capacitor as close to the device as possible. 24 in7 input voltage 7. select undervoltage threshold using th0?h4. see table 2. for improved noise immunity, bypass in7 to gnd with a 0.1? capacitor as close to the device as possible.
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 9 pin description (continued) pin MAX6892 max6893 max6894 name function 25 21 in6 input voltage 6. select undervoltage threshold using th0?h4. see table 2. for improved noise immunity, bypass in6 to gnd with a 0.1? capacitor as close to the device as possible. 26 22 in5 input voltage 5. select undervoltage threshold using th0?h4. see table 2. power the device through in2?n5 or v cc (see the powering the MAX6892/max6893/max6894 section). for improved noise immunity, bypass in5 to gnd with a 0.1? capacitor as close to the device as possible. 27 23 23 in4 input voltage 4. select undervoltage threshold using th0?h4. see table 2. power the device through in2?n5 or v cc (see the powering the MAX6892/max6893/max6894 section). for improved noise immunity, bypass in4 to gnd with a 0.1? capacitor as close to the device as possible. 28 24 24 in3 input voltage 3. select undervoltage threshold using th0?h4. see table 2. power the device through in2?n5 or v cc (see the powering the MAX6892/max6893/max6894 section). for improved noise immunity, bypass in3 to gnd with a 0.1? capacitor as close to the device as possible. 29 25 25 in2 input voltage 2. select undervoltage threshold using th0?h4. see table 2. power the device through in2?n5 or v cc (see the powering the MAX6892/max6893/max6894 section). for improved noise immunity, bypass in2 to gnd with a 0.1? capacitor as close to the device as possible. 30 26 26 in1 input voltage 1. select undervoltage threshold using th0?h4. see table 2. for improved noise immunity, bypass in1 to gnd with a 0.1? capacitor as close to the device as possible. 31 27 27 wdi watchdog timer input. logic input for the watchdog timer function. if wdi is not strobed with a valid low-to-high or high-to-low transition within the watchdog timeout period, the watchdog output asserts low. the watchdog timeout period is externally adjustable with capacitor c swt or selectable for a fixed internal timeout period. the watchdog has a long timeout period (92.16s minimum fixed or 64x the adjusted short timeout period) after each reset event and a short timeout period (1.44s minimum or an adjusted timeout period) after the first valid wdi transition. 32 28 28 pg1 open-drain, power-good output 1. pg1 asserts low when the voltage input at in1 is below the pin-selectable/adjustable input threshold or enable is pulled high. pg1 deasserts with a factory preset timeout period of 6.25ms. 5, 6, 21, 22 n.c. no connection. not internally connected. ep ep ep gnd exposed paddle. internally connected to gnd. connect ep to gnd or leave floating.
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 10 ______________________________________________________________________________________ functional diagram logic array woi enable margin mr v ref in2 detector in3 detector in4 detector in5 detector in6 detector in1 in3 in4 in5* in6* in2 in_ detector pg2 output pg3 output pg4 output pg5 output pg6 output pg7 output pg8 output pg2 swt dbp dbp srt pg3 pg4 pg5* pg6* pg7** pg8 pg1 10 a power-up pulldown 1 f 1 f threshold selection logic th1 th0 th2 th3 th4 gnd * for MAX6892/max6893 only. ** for MAX6892 only. in7 detector in7** in8 detector in8** wdo output reset output wdo reset open-drain active-low pg_ output 2.55v ldo dbp (virtual diodes) v cc MAX6892 max6893 max6894
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 11 detailed description the MAX6892/max6893/max6894 pin-selectable, mul- tivoltage supply sequencers/supervisors monitor sever- al voltage detector inputs and one watchdog input, asserting the outputs when the respective input thresh- olds have been reached or a timeout occurs. all ver- sions have an enable manual reset and margin input disable. the MAX6892/max6893/max6894 voltage thresholds are selected by logic inputs and/or an exter- nal voltage-divider. a reset output ensures all moni- tored inputs are above the pin-selected/adjustable thresholds. watchdog and reset timeout periods can use factory default settings or are independently adjustable by connecting external capacitors. in addi- tion, all devices can be powered through the voltage detector inputs alone, or externally supplied from a constant supply on the v cc pin (see the powering the MAX6892/max6893/max6894 section). the outputs are factory configured as open drain. powering the MAX6892/max6893/max6894 the MAX6892/max6893/max6894 derive power from the voltage detector inputs: in2?n5 (MAX6892/ max6893), in2?n4 (max6894), or through an external- ly supplied v cc . a virtual diode-oring scheme selects the positive input that supplies power to the device (see the functional diagram ). the highest input voltage on in2?n5 (MAX6892/max6893)/in2?n4 (max6894) supplies power to the device. one of in2?n5 (max6889/max6890)/in2?n4 (max6891) or v cc must be at least 2.7v to ensure proper operation. internal hysteresis ensures that the supply input that initially powered the device continues to power the device when multiple input voltages are within 50mv of each other. v cc powers the analog circuitry and is the bypass con- nection for the MAX6892/max6893/max6894 internal supply. bypass v cc to gnd with a 1? ceramic capac- itor installed as close to the device as possible. the internal supply voltage, measured at v cc , equals the maximum of in2?n5. if v cc is externally supplied, v cc must be at least 200mv higher than any voltage applied to in2?n5 and v cc must be brought up first. v cc always powers the device when all in_ are factory set as ?dj.?do not use the internally generated v cc to provide power to external circuitry. the MAX6892/max6893/max6894 also generate a dig- ital supply voltage (dbp) for the internal logic circuitry and the output stages. bypass dbp to gnd with a 1? ceramic capacitor installed as close to the device as possible. the nominal dbp output voltage is 2.55v. do not use dbp to provide power to external circuitry. inputs the MAX6892/max6893/max6894 contain multiple logic and voltage detector inputs. each voltage detec- tor input is monitored for undervoltage thresholds. voltage detector inputs (in_) the MAX6892/max6893/max6894 offer several moni- tor options with both pin-selectable and adjustable reset thresholds. the threshold voltage at each adjustable in_ input is typically 0.6v. to monitor a volt- age >0.6v, connect a resistor-divider network to the circuit as shown in figure 1: v in_th = v th (r 1 + r 2 ) / r 2 (equation 1) where v in_th is the desired reset threshold voltage for the respective in_ and v th is the input threshold (0.6v). resistors r 1 and r 2 can have high values to minimize current consumption due to low-leakage currents. set r 2 to some conveniently high value (10k ? , for exam- ple) and calculate r 1 based on the desired reset threshold voltage, using the following formula: r 1 = r 2 x (v in_th /v th - 1) in_ gnd v cc v cc v in_th v in_th = 0.6 x (r 1 + r 2 ) / r 2 r 1 r 2 MAX6892 max6893 max6894 figure 1. adjusting the monitored threshold
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 12 ______________________________________________________________________________________ threshold logic inputs (th0?h4) the th0?h4 logic inputs select the undervoltage thresh- olds and tolerance of the in1?n8 inputs (MAX6892), in1?n6 inputs (max6893), and in1?n4 inputs (max6894). th0?h4 define 32 unique options for the supervisor functionality. connect the respective th_ to gnd for a logic 0 or to dbp for a logic 1. tables 1 and 2 show the 32 unique threshold options available. th4 sets the threshold tolerance of the undervoltage threshold. a logic 1 selects a 5% supply tolerance and a logic 0 selects 10% supply tolerance. the MAX6892/max6893/ max6894 logic determines which thresholds should be used for the in inputs only at power-up. use the voltage- divider circuit of figure 1 and equation 1 to set the threshold for the user-adjustable inputs as described in the voltage detector inputs (in_) section. table 1. nominal monitored supply voltages monitored supply voltages (v) selection th4?h0 in1 in2 in3 in4 in5 in6 in7 in8 supply tolerance (%) 1 11111 adj 5 3.3 2.5 1.8 adj adj adj 5 2 11110 adj 5 3 2.5 1.8 adj adj adj 5 3 11101 adj 5 3.3 2.5 adj adj adj adj 5 4 11100 adj 5 3 2.5 adj adj adj adj 5 5 11011 adj 5 3.3 1.8 adj adj adj adj 5 6 11010 adj 5 3 1.8 adj adj adj adj 5 7 11001 adj 5 3.3 adj adj adj adj adj 5 8 11000 adj 5 3 adj adj adj adj adj 5 9 10111 adj 3.3 2.5 1.8 adj adj adj adj 5 10 10110 adj 3 2.5 1.8 adj adj adj adj 5 11 10101 adj 3.3 2.5 adj adj adj adj adj 5 12 10100 adj 3 2.5 adj adj adj adj adj 5 13 10011 adj 3.3 1.8 adj adj adj adj adj 5 14 10010 adj 3 1.8 adj adj adj adj adj 5 15 10001 adj 3.3 2.5 1.8 1.5 adj adj adj 5 16 10000 adj 3 2.5 1.8 1.5 adj adj adj 5 17 01111 adj 5 3.3 2.5 1.8 adj adj adj 10 18 01110 adj 5 3 2.5 1.8 adj adj adj 10 19 01101 adj 5 3.3 2.5 adj adj adj adj 10 20 01100 adj 5 3 2.5 adj adj adj adj 10 21 01011 adj 5 3.3 1.8 adj adj adj adj 10 22 01010 adj 5 3 1.8 adj adj adj adj 10 23 01001 adj 5 3.3 adj adj adj adj adj 10 24 01000 adj 5 3 adj adj adj adj adj 10 25 00111 adj 3.3 2.5 1.8 adj adj adj adj 10 26 00110 adj 3 2.5 1.8 adj adj adj adj 10 27 00101 adj 3.3 2.5 adj adj adj adj adj 10 28 00100 adj 3 2.5 adj adj adj adj adj 10 29 00011 adj 3.3 1.8 adj adj adj adj adj 10 30 00010 adj 3 1.8 adj adj adj adj adj 10 31 00001 adj 3.3 2.5 1.8 1.5 adj adj adj 10 32 00000 adj adj adj adj adj adj adj adj
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 13 table 2. threshold options threshold voltages (v) selection th4?h0* in1 in2 in3 in4 in5 in6 in7 in8 1 11111 0.60 4.62 3.06 2.31 1.67 0.60 0.60 0.60 2 11110 0.60 4.62 2.78 2.31 1.67 0.60 0.60 0.60 3 11101 0.60 4.62 3.06 2.31 0.60 0.60 0.60 0.60 4 11100 0.60 4.62 2.78 2.31 0.60 0.60 0.60 0.60 5 11011 0.60 4.62 3.06 1.67 0.60 0.60 0.60 0.60 6 11010 0.60 4.62 2.78 1.67 0.60 0.60 0.60 0.60 7 11001 0.60 4.62 3.06 0.60 0.60 0.60 0.60 0.60 8 11000 0.60 4.62 2.78 0.60 0.60 0.60 0.60 0.60 9 10111 0.60 3.06 2.31 1.8 0.60 0.60 0.60 0.60 10 10110 0.60 2.78 2.31 1.8 0.60 0.60 0.60 0.60 11 10101 0.60 3.06 2.31 0.60 0.60 0.60 0.60 0.60 12 10100 0.60 2.78 2.31 0.60 0.60 0.60 0.60 0.60 13 10011 0.60 3.06 1.67 0.60 0.60 0.60 0.60 0.60 14 10010 0.60 2.78 1.67 0.60 0.60 0.60 0.60 0.60 15 10001 0.60 3.06 2.31 1.67 1.39 0.60 0.60 0.60 16 10000 0.60 2.78 2.31 1.67 1.39 0.60 0.60 0.60 17 01111 0.60 4.38 2.88 2.19 1.58 0.60 0.60 0.60 18 01110 0.60 4.38 2.62 2.19 1.58 0.60 0.60 0.60 19 01101 0.60 4.38 2.88 2.19 0.60 0.60 0.60 0.60 20 01100 0.60 4.38 2.62 2.19 0.60 0.60 0.60 0.60 21 01011 0.60 4.38 2.88 1.58 0.60 0.60 0.60 0.60 22 01010 0.60 4.38 2.62 1.58 0.60 0.60 0.60 0.60 23 01001 0.60 4.38 2.88 0.60 0.60 0.60 0.60 0.60 24 01000 0.60 4.38 2.62 0.60 0.60 0.60 0.60 0.60 25 00111 0.60 2.88 2.19 1.8 0.60 0.60 0.60 0.60 26 00110 0.60 2.62 2.19 1.8 0.60 0.60 0.60 0.60 27 00101 0.60 2.88 2.19 0.60 0.60 0.60 0.60 0.60 28 00100 0.60 2.62 2.19 0.60 0.60 0.60 0.60 0.60 29 00011 0.60 2.88 1.58 0.60 0.60 0.60 0.60 0.60 30 00010 0.60 2.62 1.58 0.60 0.60 0.60 0.60 0.60 31 00001 0.60 2.88 2.19 1.58 1.31 0.60 0.60 0.60 32 00000 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 * th4 = ??selects 7.5% threshold tolerance, th4= ??selects 12.5% threshold tolerance. contact factory for alternative thresholds.
wdi t rp *t wdi *t wdi t wd t d-po t rp t rp *t wdi *t wdi t wd t d-po wdo not connected to mr wdo connected to mr. v cc or in2?n5 2.5v wdi v cc or in2?n5 2.5v *t wdi is the initial watchdog timeout period. reset wdo wdo reset figure 2. watchdog, reset, and power-up timing diagram MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 14 ______________________________________________________________________________________ watchdog timer the MAX6892/max6893/max6894s?watchdog circuit monitors the microprocessor? (p?) activity. if the ? does not toggle the watchdog input (wdi) within the watchdog timeout period, the watchdog output ( wdo ) asserts. the internal watchdog timer is cleared by reset , or by a transition at wdi (which can detect pulses as short as 50ns). the watchdog timer remains cleared while reset is asserted. the timer starts count- ing as soon as wdo is released (see figure 2). the MAX6892/max6893/max6894 feature two modes of watchdog timer operation: normal mode and initial mode. at power-up, after a reset event, or after the watchdog timer expires, the initial watchdog timeout is active. after the first transition on wdi, the normal watchdog timeout is active. the initial and normal watchdog timeouts are determined by the value of the capacitor connected between swt and ground or by connecting swt to v cc (see the selecting the reset and watchdog timeout capacitor section). the initial watch- dog timeout is approximately 64 times the normal watch- dog timeout. for example, in initial mode a 1f capacitor gives a watchdog timeout period of about 5min. if wdo is connected to mr, the wdo asserts for a short duration (~5?), long enough to assert the reset output. asserting reset clears the watchdog timer and wdo goes high. the reset output remains asserted for its timeout period after a watchdog fault. the watchdog timer stays cleared as long as reset is low. the watchdog timeout period is determined by the value of the capacitor connected between swt and ground (see the selecting the reset/watchdog timeout capacitor section). connect swt to dbp to select fac- tory-programmed watchdog timeout. to disable the watchdog timer connect swt to gnd.
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 15 manual reset ( mr ) many ?-based products require manual reset capabil- ity to allow an operator or external logic circuitry to initi- ate a reset. the manual reset input ( mr ) can connect directly to a switch without an external pullup resistor or debouncing network. mr is internally pulled up to dbp through a 10? current source and, therefore, can be left unconnected if unused. mr is designed to reject fast falling transients (typically 100ns pulses) and it must be held low for a minimum of 1? to assert reset . after mr transitions from low to high, reset remains asserted for the duration of the reset timeout period. margin output disable ( margin ) margin allows system-level testing while power sup- plies exceed the normal ranges. driving margin low forces pg_, reset , and wdo to hold the last state while system-level testing occurs. leave margin unconnected or connect to dbp if unused. an internal 10? current source pulls margin to dbp. the state of each programmable output, reset , and wdo does not change while margin = gnd. enable input enable is an active-high, logic input. driving enable high pulls all pg_ low. drive enable high or leave floating for normal operation. enable is internally pulled down to gnd through a 10? current sink. power-good outputs the MAX6892 features eight power-good outputs, the max6893 features six power-good outputs, and the max6894 features four power-good outputs. each out- put (pg_) responds to its respective input (in_). each pg_ is open drain. during power-up, the outputs pull down to gnd with an internal 10? current sink for 1v < v cc < v uvlo . r r e e s s e e t t output the reset output is typically connected to the reset input of a ?. a ?? reset input starts or restarts the ? in a known state. the MAX6892/max6893/max6894 supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions. reset changes from high to low whenever one or more input voltage (in1?n8) monitors drop below their respective reset threshold voltage or when mr is pulled low for a minimum of 1?. once the affected input volt- age monitor(s) exceeds its respective reset threshold voltage(s), reset remains low for the reset timeout period, then deaaserts. applications information selecting the reset/watchdog timeout capacitor the reset timeout period can be adjusted to accommo- date a variety of ? applications. adjust the reset time- out period (t rp ) by connecting a capacitor (c srt ) between srt and ground. calculate the reset timeout capacitor as follows: c srt = t rp / (4.348 x 106) with t rp in seconds and c srt in farads. connect srt to v cc for a factory-programmed reset timeout of 200ms (typ). the watchdog timeout period can be adjusted to accommodate a variety of ? applications. with this feature, the watchdog timeout can be optimized for software execution. the programmer can determine how often the watchdog timer should be serviced. adjust the watchdog timeout period (t wd ) by connect- ing a specific value capacitor (c swt ) between swt and gnd. for normal mode operation, calculate the watchdog timeout capacitor as follows: c swt = t wd / (4.348 x 10 6 ) with t wd in seconds and c swt in farads. connect swt to v cc for a factory-programmed watchdog timeout of 1.6s (normal mode) and 102.4s (initial mode). c srt and c swt must be a low-leakage (<10na) type capacitor. ceramic capacitors are recommended. layout and bypassing for better noise immunity, bypass each of the voltage detector inputs to gnd with 0.1? capacitors installed as close to the device as possible. bypass v cc and dbp to gnd with 1? capacitors installed as close to the device as possible.
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 16 ______________________________________________________________________________________ pin configuration (continued) 28 27 26 25 24 23 22 8910 11 12 13 16 17 18 19 20 21 7 6 5 4 3 2 1 max6893 thin qfn top view pg3 pg2 pg4 gnd pg5 pg6 reset *exposed paddle *exposed pad internally connected to gnd. pg1 wdi in1 in2 in3 in4 in5 in6 dbp v cc enable srt swt 15 th4 th2 th1 14 th3 th0 mr margin wdo 28 27 26 25 24 23 22 8910 11 12 13 16 17 18 19 20 21 7 6 5 4 3 2 1 max6894 thin qfn top view pg3 pg2 pg4 gnd n.c. n.c. reset *exposed paddle *exposed pad internally connected to gnd. pg1 wdi in1 in2 in3 in4 n.c. n.c. dbp v cc enable srt swt 15 th4 th2 th1 14 th3 th0 mr margin wdo chip information process: bicmos
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 17 max6893 5v supply pg2 pg3 pg4 5v bus input t pg2 t pg3 t pg4 t pg5 enable 3.3v dc-dc converter 3.3v supply 3.3v output enable 1.8v dc-dc converter 1.8v supply 1.8v output enable 2.5v dc-dc converter 2.5v supply pg5 reset 2.5v output enable 1.5v dc-dc converter 1.5v supply 1.5v output t reset dc-dc 1 dbp th0 th1 th2 th3 th4 pg2 in2 in1 dc-dc 2 in3 pg3 dc-dc 3 in4 pg4 pg5 gnd in5 in6 1.5v 1.8v 2.5v 5v 3.3v 5v wdi wdo reset reset mr margin logic output logic input pg1 pg6 srt swt v cc c srt c swt enable system reset dc-dc 4 p t ypical operating circuit
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors 18 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e xxxxx marking g 1 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale- l
MAX6892/max6893/max6894 pin-selectable, octal/hex/quad, power-supply sequencers/supervisors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 no no no no no no no no yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 y 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 n 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 y 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. g 2 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only.

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